The present invention relates to a semiconductor integrated circuit and, particularly, to a semiconductor integrated circuit including a plurality of sequencers.
Sequencers are often used in a semiconductor integrated circuit that is included in a video processing device, a communication device or the like to which data is successively input and that sequentially performs predetermined processing on the input data. Suggestions from various points of view have been made for such a semiconductor integrated
For example, Japanese Unexamined Patent Application Publication No. H06-253157 discloses a technique that divides a control block into a total control block for control in units of lines and a control block for control in units of codewords and incorporates sequence control in units of codewords into a coding operation block in order to achieve speed enhancement and cost reduction of a binary picture signal coding LSI (semiconductor integrated circuit). This is described with reference to FIG. 14.
FIG. 14 corresponds to FIG. 1 of Japanese Unexamined Patent Application Publication No. H06-253157, through the reference symbols of the functional blocks are altered. Referring to FIG. 14, a coding LSI 31 includes a system bus I/F 33 that makes a connection to a control MPU 42, a total control sequencer 32 that is connected to the control MPU 42 through the system bus I/F 33, an image bus I/F 34, a line memory unit 35, and a coding operation unit 40. The coding operation unit 40 includes a change detection and mode determination processing unit 36, a code generation unit 37, a code packing unit 38, and a code output FIFO 39, which perform pipeline processing.
Image data is input to the line memory unit 35 from an image data input device 41 through the image bus I/F 34, output from the line memory unit 35 to the change detection and mode determination processing unit 36 of the coding operation unit 40, then processed by the change detection and mode determination processing unit 36, the code generation unit 37, the code packing unit 38 and the code output FIFO 39, and finally output to a code bus.
The respective functional blocks included, in the coding operation unit 40 include block sequencers that control processing performed by the corresponding functional blocks, and those block sequencers are controlled by the total control sequencer 32. Note that the total control sequencer 32 mainly performs control of start/stop of processing of each block sequencer, and each block sequencer performs control specialized to processing performed by the corresponding functional block.
Japanese Unexamined Patent Application Publication No. H10-198421 discloses a device for monitoring a failed state of a sequencer that is installed in a coal handling facility. The device is described with reference to FIG. 15.
FIG. 15 corresponds to FIG. 1 in Japanese Unexamined Patent Application Publication No. H10-198421. A failed state monitoring device 10 in FIG. 15 includes a CPU 11 that constitutes a monitoring control device, and two input devices 13 for the CPU 11. The two input devices 13 are composed of a signal transmission unit, and an on/off signal of a sequencer contact is output from a sequencer 12 of each of two coal handling lines A and B to a storage device 14 of the CPU 11.
According to Japanese Unexamined Patent Application Publication No. H10-198421, it is disclosed that the device can input the on/off signal for a contact of the sequencer 12 to the storage device 14 in correspondence to a cause of failure and store the signal in a hierarchical manner, display that there is a failure in a hierarchy level containing the cause of failure and a hierarchy level on its higher side on a display 15, and, based on the display, perform expansion from the higher level to the lower level by a mouse 17 repeatedly so as to examine the cause of failure, thereby finding the cause of failure easily without decoding a sequencer program.
In recent years, a demand for speeding up of a video processing device, a communication device and the like is ever increasing, and, accordingly, a system LSI that is used for such a device is experiencing an increase in the number of parallel processing and in circuit size. Further, for design of the system LSI, addition of a new functional block, an increase in the number of parallel processing of functional blocks, segmentation of a control method for a functional block and so on are required to enhance the performance in view of the applications, the customer needs, the market situation or the like, and various modifications are made to meet such requirements.
In such a background, a control architecture for achieving the easiness of the above-described modifications is required.